Currently, the demands of higher-performance electronic circuits are increasing since the related technologies have been rapidly developed. As a result, a frequency divider, such as a divide-by-two circuit (DTC) has been widely used in the electronic circuits to meet the demands in different fields (e.g., global positioning system (GPS) receiver, code division multiple access (CDMA) transceiver, etc.).
FIG. 1 is a block diagram of a conventional DTC 100. The DTC 100 can employ two identical latch circuits (e.g., latch circuits 110 and 120). An output of one latch circuit is sent to an input of the other latch circuit, and vice versa. Each latch circuit is controlled by a pair of complementary clock signals CLKP and CLKN, and has a pair of input terminals (DP and DN) and a pair of output terminals (QP and QN).
FIG. 2 is a block diagram of a conventional latch circuit 200 in a DTC (e.g., the latch circuit 110 or 120 in the DTC 100). The latch circuit 200 can include a number of successive levels of circuits in a direction from ground to a source voltage VDD. The first level includes a NMOS transistor 210 functioning as a current source. The NMOS transistor 210 has a source terminal coupled to ground and a gate terminal receiving a control voltage VBIASN. In the first level, a current IPRES (that can be also called a source current) flows through the NMOS transistor 210 when the NMOS transistor 210 operates in an active region. The second level includes source-coupled NMOS transistors 220 and 222 with their source terminals coupled to a drain terminal of the NMOS transistor 210 and their respective gate terminals coupled to a pair of complementary clock signals CLKP and CLKN. The third level includes a first and second sub-circuits coupled in parallel. The first sub-circuit includes a pair of source-coupled NMOS transistors 230 and 232 that can receive the input signals DP and DN. A drain terminal of the NMOS transistor 230 is bridged to the source voltage VDD via a serial resistor 240 and a drain terminal of the NMOS transistor 232 is bridged to the source voltage VDD via a serial resistor 242. The second sub-circuit includes a pair of cross-coupled NMOS transistors 231 and 233. The drain terminals of the NMOS transistors 230 and 231 are coupled to a gate terminal of the NMOS transistor 233. The-drain terminals of the NMOS transistors 232 and 233 are coupled to a gate terminal of the NMOS transistor 231.
The output signal QP is logic high (e.g., VDD) and the output signal QN is logic low (e.g., VDD−IPRES*R1) when the NMOS transistor 230 is turned on and the NMOS transistor 232 is turned off. Similarly, the output signal QP is logic low (e.g., VDD−IPRES*R2) and the output signal of QN is logic high (e.g., VDD) when the NMOS transistor 230 is turned off and the NMOS transistor 232 is turned on. Therefore, a voltage swing of the output signal QN is a difference between logic high and logic low, which can be given by equation (1).VSWING=VHIGH−VLOW=VDD−(VDD−IPRES*R1)=IPRES*R1  (1)VSWING represents the voltage swing of the output signal QN. VHIGH represents a voltage value of QN when the output signal QN is logic high. VLow represents a voltage value of QN when the output signal QN is logic low. R1 represents the resistance of the serial resistor 240. Similarly, a voltage swing of the output signal QP can be equal to IPRES*R2. R2 represents the resistance of the serial resistor 242.
FIG. 3 is a block diagram of a conventional bias circuit 300 for controlling a latch circuit (e.g., the latch circuit 200). The bias circuit 300 can provide a voltage VBIASN to the gate terminal of the NMOS transistor 210. The bias circuit 300 includes gate-coupled PMOS transistors 310 and 312 with their source terminals coupled to the source voltage VDD. A drain terminal of the PMOS transistor 310 is coupled to ground through a serial resistor 320 and a drain terminal of the PMOS transistor 312 is coupled to ground through a NMOS transistor 322.
The bias circuit 300 also includes an operational amplifier 330 with its output terminal coupled to the gate terminal of the PMOS transistor 310 and its positive input terminal coupled to the drain terminal of the PMOS transistor 310. An input reference voltage is received by the operational amplifier 330 and the drain voltage of the PMOS transistor 310 is forced to be equal to the input reference voltage. Since the PMOS transistors 310 and 312 form a current mirror and the size of the PMOS transistor 310 is equal to that of the PMOS transistor 312, the current flowing through the PMOS transistor 312 can be equal to the current flowing through the serial resistor 320. The current flowing through the NMOS transistor 210 can be equal to the current flowing though the serial resistor 320 when the NMOS transistor 210 has a same size as the NMOS transistor 322, as shown by equation (2).IPRES=VREF/RREF  (2)VREF represents the input reference voltage at the negative terminal of the operational amplifier 330. RREF represents the resistance of the serial resistor 320.
Therefore, the voltage swing of the output signal QN in FIG. 2 can be obtained by equation (3).VSWING=IPRES*R1=VREF*(R1/RREF)  (3)
FIG. 4 is a structure diagram of a conventional NMOS transistor 400 in a latch circuit (e.g., the latch circuit 200). The NMOS transistor 400 can be any of the NMOS transistors 210, 220, 222, and 230-233. The NMOS transistor 400 is manufactured in a common p-substrate coupled to ground. And there are voltage differences between bulks (e.g., the p-substrate) and the source terminals of the NMOS transistors 220, 222, and 230-233. For example, a voltage difference between the bulk and the source terminal of the NMOS transistor 220 or 222 can be equal to a voltage difference between the drain terminal and the source terminal the NMOS transistor 210, e.g., VDS—210. The voltage difference between the bulk and the source terminal of the NMOS transistor 230, 231, 232, or 233 can be equal to a summation of the voltage difference between the drain terminal and the source terminal of the NMOS transistor 210 and a voltage difference between the drain terminal and the source terminal of the NMOS transistor 220 or 222, e.g., VDS—210+VDS—220 or VDS—210+VDS—222. Accordingly, threshold voltages of the NMOS transistors 220, 222, and 230-233 are increased as a result of body-bias effect. Due to the body-bias effect, a relatively high voltage swing for the clock signals CLKP and CLKN is required to fully turn on and turn off the NMOS transistors 220 and 222. Therefore, it may be difficult to decrease the voltage of a power source (e.g., VDD). The higher voltage swing can also impose limitations on previous stages (not shown) which are coupled to the DTC 100 in FIG. 1. For example, in order to maintain the desirable speed performance, the DTC 100 may require a higher current from the previous stages. In this condition, an extra buffer may be needed to be coupled between the previous stages and the DTC 100 in order to provide a required output voltage swing of the DTC 100.
FIG. 5 is a structure diagram of a conventional isolated NMOS transistor 500 in a latch circuit (e.g., the latch circuit 200). The isolated NMOS transistor 500 can be employed to substitute the NMOS transistor 400 used in the latch circuit 200 to eliminate the drawbacks introduced by the body-bias effect resulting from the NMOS transistor 400. The isolated NMOS transistor 500 is built in a p-well, instead of directly in a p-substrate, and is electrically isolated from the p-substrate via a deep n-well. The source, gate and drain terminals of the isolated NMOS transistor 500 can be isolated from the substrate and hence the body-bias effect can be eliminated.
Although the introduction of the isolated NMOS transistor 500 can eliminate the body-bias effect, it can also introduce parasitic capacitance in the latch circuit 200. The parasitic capacitance introduced by the isolated NMOS transistor 500 can be substantially higher than the parasitic capacitance introduced by the NMOS transistor 400. Due to the parasitic capacitance introduced by the isolated NMOS transistor 500, the performance of the latch circuit 200 with the isolated NMOS transistor 500 can be limited.